# -----------------------------------------------------------------------------
# Copyright (c) 2025, Southeast University (China)
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#  - Redistributions of source code must retain the above copyright
#    notice, this list of conditions and the following disclaimer.
#  - Redistributions in binary form must reproduce the above copyright
#    notice, this list of conditions and the following disclaimer in the
#    documentation and/or other materials provided with the distribution.
#  - Neither the name of the copyright holders nor the names of its
#    contributors may be used to endorse or promote products derived from
#    this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Jiajie Xu, Yanfang Zhang, Jiaqi Gao, Leyun Tian
# -----------------------------------------------------------------------------


# Set multiple threds
set_parameter max_thread_number {1}

# Create Workspace
create_workspace TSMC12 -overwrite 

set top_design sasc_top

# Link LEF files: technology lef and all cell lef
link_reference_library -format lef "/home/techlibs/TSMC/12nm/standcell/9t/tcbn12ffcllbwp16p90_100a/0M18012_20230605/TSMCHOME/digital/Back_End/lef/tcbn12ffcllbwp16p90_100a/lef/tcbn12ffcllbwp16p90.lef \
                                    /home/techlibs/TSMC/12nm/standcell/9t/tcbn12ffcllbwp16p90lvt_100a/0M18012_20230605/TSMCHOME/digital/Back_End/lef/tcbn12ffcllbwp16p90lvt_100a/lef/tcbn12ffcllbwp16p90lvt.lef \
                                    /home/techlibs/TSMC/12nm/standcell/9t/tcbn12ffcllbwp16p90ulvt_100a/0M18012_20230605/TSMCHOME/digital/Back_End/lef/tcbn12ffcllbwp16p90ulvt_100a/lef/tcbn12ffcllbwp16p90ulvt.lef \
                                    /home/jiajiexu/mylib/Innovus_Lab/TSMC12/outdata/${top_design}.lef"

# Auto create design for physical hierarchical design
define_designs -verilogs "/home/jiajiexu/mylib/Innovus_Lab/TSMC12/outdata/${top_design}.v" -defs "/home/jiajiexu/mylib/Innovus_Lab/TSMC12/outdata/${top_design}.def"

# Set site map
#set_site_map {unit core}
#set_site_map -design blockA {unit core9T}
#set_site_map -design blockB {unit core6T}

# Set removable fillers
set_removable_fillers {FILL*} ;# specify lib cell name pattern of removable fillers.

# Import design date
import_designs

# Import power domain information
#import_power_domain -design "top" -upf_file "top.upf" -region_file "top.pd"
#import_power_domain -design "blockA" -upf_file "blockA.upf" -region_file "blockA.pd"

# Check placement readiness
check_placement_readiness

# Save workspace
save_workspace
#exit
